Field of the Invention
The disclosed technology relates generally to semiconductor devices, and more particularly to fin-shaped field-effect transistors (finFETs).
Description of the Related Art
Physical scaling of transistors continues to pose new challenges at each technology generation. Technological innovations such as strain engineering (e.g., strained silicon) and alternative materials (e.g., high-K gate dielectric and metal gates) have enabled manufacturers to continue to scale transistors to have channel lengths as short as 20-30 nm. For high performance logic applications, proposed paths to physical scaling of transistors to have channel lengths below 20-30 nm include silicon-on-insulator (SOI) technologies, in which transistor channels are formed using ultrathin silicon layers formed on a buried insulator layer to further scale the transistors, and multigate transistors such as dual-gate and tri-gate transistors, in which two- or three-dimensional transistor channels are formed using thin slab (e.g., vertical fin-shaped) structures. For the latter approach, scaling the physical dimensions (e.g., height, width) of the channel regions of the transistors in both vertical and horizontal directions while maintaining high on current and ON/OFF ratios remain a challenge.